(1)Field of the Invention
The invention relates to a method to manufacture an integrated circuit device, and, more particularly, to a method to roam a floating gate for a stacked gate flash memory in the manufacture of an integrated circuit device.
(2) Description of the Prior Art
Non-volatile memory devices are widely used in the art of electronics. Non-volatile memories provide-stored data to an electronic system in a form that can be retained even during a loss of system power. Non-volatile memory can take the form of one-time programmable devices, such as electrically programmable read-only memory (EPROM), or re-programmable devices, such as electrically erasable, programmable read-only memory (EEPROM). A particular type of EEPROM that is of interest in the present invention is the flash EEPROM. A flash EEPROM provides a means to rapidly erase the EEPROM memory array prior to programming or re-programming.
Referring now to FIG. 1, exemplary flash EEPROM device is shown in cross sectional representation. A flash device is a MOSFET device where a complex gate 14 is used. The complex gate comprises a floating gate 18 and a control gate 22. The floating gate comprises a first conductor layer 18 overlying the substrate 10 with a gate dielectric layer 16 therebetween. The control gate comprises a second conductor layer 22 in close proximity to the floating gate 18 and with a second dielectric layer 20 lying between-the first and second conductor layers 18 and 22. Further, the example device is a stacked gate device. In a stacked gate device, the channel region of the substrate 10—the region of the substrate 10 between the drain region 24 and the source region 26—is controlled indirectly by the control gate 22. In the flash device, the memory transistor is turned ON —such that current can conduct from drain 24 to source 26—when the control gate 22 bias is large enough to invert the entire channel region. As a result, a voltage bias on the control gate 22 is divided across the series capacitance of the floating gate 18 prior to interacting with the channel.
The flash device exhibits two, distinct states: programmed and erased. In the erased state, the floating gate 18 is devoid of excess electron charge. In the programmed state, the floating gate 18 has a large amount of excess electron charge trapped on the first conductor layer 18. The presence of excess electron charge on the floating gate increases the effective threshold voltage (Vth) of the device. That is, a larger gate voltage must be applied to the control gate 22 to turn ON the flash device in the programmed (excess electron) state than in the erased state (no excess electrons) state. In the applied circuit, a current sensing mechanism is used to determine the ON-OFF state of the device in the presence of a standard control voltage and a drain-to-source voltage. The determined ON-OFF state is used to “read” the stored data state of the cell as a “0” or “1”. Alternatively, in a multiple-state device, any of several threshold voltages Vth may by stored by trapping various, relative amounts of charge on the floating gate 18.
Erasing, programming, and reading of the flash device are illustrated in FIG. 1. Erasing is accomplished by grounding the control gate 22 and the drain 24, while the source 26 is forced to a large programming voltage (VPP). As a result, electrons on the floating gate 18 are attracted toward the source 26. Due to the large erasing voltage (VPP), electrons will tunnel through the thin, gate oxide layer 16 and enter the source 26. The floating gate 18 is thereby erased by removal of electrons. Programming is performed by forcing a drain-to-source voltage by grounding the source 26 and forcing the drain 24 to Vd. The control gate 22 is forced to a gate voltage Vd that is larger than the drain-to-source voltage Vd. During programming, electrons are injected, due to impact ionization, through the thin, gate dielectric layer 16 and into the floating gate 18. The floating gate 18 is thereby programmed by addition of electrons. The stacked gate flash device is read by forcing a reading voltage of, for example, VCC, onto the control gate 22 during a drain-to-source voltage of, for example, about 1 Volt. The drain current of the device is monitored to determine if the device is ON or OFF to thereby determine the threshold voltage of the device. It is found in the art that the stacked gate device exhibits relatively poor erasing efficiency. In addition, the stacked gate flash device requires a relatively large programming voltage Vpp for erasing. Finally, the stacked gate flash can exhibit incomplete erasing due to the inefficiency of the design.
Referring now to FIG. 2, a split-gate flash device is shown. The split-gate device can achieve rapid programming and erasing times while exhibiting very stable and long enduring data retention. In the split-gate structure, part of the control gate 40 directly overlies the floating gate 34 while another part of the control gate 40 directly overlies the substrate 30 without floating gate 34 intervening. By forming a part of the control gate 40 directly over the channel region of the substrate 30, the split-gate device provides significantly better performance during an over-erase event. In an over-erase event, the floating gate 34 is discharged beyond a neutral condition.
The floating gate 34 is erased by forcing a large, programming voltage Vpp of about 14 Volts onto the control gate 40 while the drain 44 and the source 42 are grounded. Electrons are pulled from the floating gate 34 to the control gate 40 to cause the floating gate to become discharged. If the floating gate 34 is overly discharged, then the floating gate 34 will actually contain too little electron charge. This will cause the Vth of the device to fall. If the floating gate 34 is over-erased far enough, then device will become a depletion device where the channel is effectively ON all of the time even in the absence of a positive voltage on the control gate 40. In a stacked gate device, an over-erase condition will cause excessive leakage current that can limit the operating performance of the cell and of the overall array. The split-gate form reduces the over-erase effect because the Vth of the device in the channel region directly underlying the control gate 40 is not affected by the over-erase condition. Therefore, the control gate 40 will hold the channel OFF during the standby state and eliminate the leakage current even if the floating gate is over-erased.
The split-gate device is programmed by forcing a large programming voltage Vpp of about 12 Volts on the drain while the control gate 40 is forced to a low programming voltage of about 1.6 Volts. The floating gate 34 is programmed by impact ionization causing electrons to tunnel through the gate oxide 32 and to charge the floating gate. The split-gate device is read by forcing a low voltage of Vcc on the control gate 40 while a reading voltage Vread of between about 1 Volt and 2 Volts is forced from drain to source. The drain current is monitored to determine the OFF-ON state of the cell based on the threshold voltage.
A second feature of the split-gate device is the use of lateral floating gate tips 35. Floating gate tips 35 cause a concentration of the electric field between the control gate 40 and the floating gate 34 during an erasing operation. As a result, the floating gate 34 can be erased more completely and more quickly than in a comparable split-gate flash device that does not have these tips 35. In this way, the erasing conditions, and especially the control gate voltage, can be made less severe and hazardous to the long-term reliability of the device. The floating gate 34 with erasing tips 35 is formed by a local oxidation of silicon (LOCOS) process performed on the polysilicon layer 34 of the floating gate. The split-gate device offers significant performance advantages over the stacked gate device. However, the split-gate device requires significantly more area per cell than the stacked gate device. Achieving a stacked gate, flash memory device exhibiting improved erasing performance is therefore a desirable outcome of the present invention.
Several prior art inventions relate to flash memory devices and methods of manufacture. U.S. Pat. No. 6,171,906 B1 to Hsieh et al discloses a split-gate flash device and method of manufacture showing a floating gate with an erasing tip formed using LOCOS. U.S. Pat. No. 6,165,845 to Hsieh et al describes a split-gate flash device and method of manufacture. An angled etch is used to create an angled floating gate prior to using LOCOS to form the floating gate tips. U.S. Pat. Nos. 6,479,859 to Hsieh et al, 6,537,896 to Furuhata, and 6,528,844 to Hopper et al also pertain to the art of the present invention.